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42129js?sam?12/2013 description the atmel ? sam d20 is a series of low-power microcontrollers using the 32-bit arm ? cortex ? -m0+ processor, and ranging from 32- to 64-pins with up to 256kb flash and 32kb of sram. the sam d20 devices operate at a maximum frequency of 48mhz and reach 2.14 coremark/mhz. they are designed for simple and intuitive migration with identical peripheral modules, hex compatible code, identical linear address map and pin compatible migration paths between all devices in the product series. all devices include intelligent and flexible peripherals, atmel event system for inter-peripheral signaling, and support for capacitive touch button, slider and wheel user interfaces. the atmel sam d20 devices provide the following features: in-system programmable flash, eight-channel event system, programmable interr upt controller, up to 52 programmable i/o pins, 32-bit real-time clock and calendar, up to eight 16-bit timer/counters (tc). the timer/counters can be configured to perfo rm frequency and waveform generation, program execution timing or input capt ure with time and frequency meas urement of digital signals. the tcs can operate in 8- or 16-bit mode, or be cascaded to form a 32-bit tc. the series provide up to six serial communication modules (sercom) that each can be configured to act as an usart, uart, spi and i 2 c up to 400khz; up to twenty-channel 350ksps 12-bit adc with programmable gain and optional ov ersampling and decimation supporting up to 16-bit resolution, one 10-bit 350ksps dac, two analog comparators with window mode, peripheral touch controller supporting up to 256 buttons, sliders, wheels, and proximity sensing; programmable watchdog timer, br own-out detector and power-on reset, and two- pin serial wire debug (swd) program and debug interface. all devices have accurate and low-power external and internal oscillators. all oscillators can be used as a source for the system clock. different clock domains can be independently configured to run at different frequencies while enabling power saving by running each peripheral at its optimal clock frequency. the sam d20 devices have two software-selectable sleep modes, idle and standby. in idle mode the cpu is stopped while all other functi ons can be kept running. in standby all clocks and functions are stopped expect those selected to continue running. the device supports sleepwalking, which is the module's ability to wake itself up and wake up its own clock, and hence perform predefined tasks without waking up the cpu. the cpu can then be only woken on a need basis, e.g. a threshold is cross ed or a result is ready. the event system supports synchronous and asynchronous events, allowing peripherals to receive, react to and send events even in standby mode. the flash program memory can be reprogra mmed in-system through the swd interface. the same interface can be used for non-intrus ive on-chip debug of application code. a boot loader running in the device can use any comm unication interface to download and upgrade the application program in the flash memory. the atmel sam d20 devices are supported with a full suite of program and system development tools, including c compilers, macro assemblers, program debugger/simulators, programmers and evaluation kits . atmel sam d20j / sam d20g / sam d20e arm-based microcontroller datasheet summary
2 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 features z processor z arm cortex-m0+ cpu running at up to 48mhz z single-cycle hardware multiplier z memories z 16/32/64/128/256kb in-system self-programmable flash z 2/4/8/16/32kb sram z system z power-on reset (por) and brown-out detection (bod) z internal and external clock options with 48mhz digital frequency locked loop (dfll48m) z external interrupt controller (eic) z 16 external interrupts z one non-maskable interrupt z two-pin serial wire debug (swd) programming, test and debugging interface z low power z idle and standby sleep modes z sleepwalking peripherals z peripherals z 8-channel event system z up to eight 16-bit timer/counters (tc), configurable as either: z one 16-bit tc with co mpare/capture channels z one 8-bit tc with compare/capture channels z one 32-bit tc with compare/capt ure channels, by using two tcs z 32-bit real time counter (rtc) with clock/calendar function z watchdog timer (wdt) z crc-32 generator z up to six serial communication interfaces (sercom), each configurable to operate as either: z usart with full-duplex and singl e-wire half-duplex configuration z i 2 c up to 400khz z spi z one 12-bit, 350ksps analog-to-digital converter (adc) with up to 20 channels z differential and single-ended channels z 1/2x to 16x gain stage z automatic offset and gain error compensation z oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution z 10-bit, 350ksps digital-to-analog converter (dac) z two analog comparators with window compare function z peripheral touch controller (ptc) z 256-channel capacitive touch and proximity sensing z i/o z up to 52 programmable i/o pins z packages z 64-pin tqfp, qfn z 48-pin tqfp, qfn z 32-pin tqfp, qfn z operating voltage z 1.62v ? 3.63v z power consumption z down to 70a/mhz in active mode z down to 8a running the peripheral touch controller
3 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 1. configuration summary sam d20j sam d20g sam d20e number of pins 64 48 32 general purpose i/o-pins (gpios) 52 38 26 flash 256/128/64/32/16kb 256/128/64/32/16kb 256/128/64/32/16kb sram 32/16/8/4/2kb 32/16/8/4/2kb 32/16/8/4/2kb maximum cpu frequency 48mhz event system channels 8 8 8 timer counter (tc) 8 6 6 waveform output channels for tc 2 2 2 serial communication interface (sercom) 6 6 4 analog-to-digital converter (adc) channels 20 14 10 analog comparators 2 2 2 digital-to-analog converter (dac) channels 1 1 1 real-time counter (rtc) yes yes yes rtc alarms 1 1 1 rtc compare values 1 32-bit value or 2 16-bit values 1 32-bit value or 2 16-bit values 1 32-bit value or 2 16-bit values external interrupt lines 16 16 16 peripheral touch controller (ptc) x and y lines 16x16 12x10 10x6 packages qfn tqfp qfn tqfp qfn tqfp oscillators 32.768khz crystal oscillator (xosc32k) 0.4-32mhz crystal oscillator (xosc) 32.768khzinternal oscillator (osc32k) 32khz ultra-low-power internal oscillator (osculp32k) 8mhz high-accuracy internal oscillator (osc8m) 48mhz digital frequency locked loop (dfll48m) sw debug interface yes yes yes watchdog timer (wdt) yes yes yes
4 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 2. ordering information 2.1 sam d20e ? atsamd ? 20 ?? e ?? 14 ?? a ??\??? m ?? u ?? t product ? family atsamd ? = ? general ? purpose ? microcontroller product ? series 20 ? = ? cortex ? m0+ ? cpu, ? general ? feature ? set flash ? memory 18 ? = ? 256kb 17 ? = ? 128kb 16 ? = ? 64kb 15 ? = ? 32kb 14 ? = ? 16kb device ? variant a ? = ? default ? variant pin ? count e ? = ? 32 ? pins g ? = ? 48 ? pins j ? = ? 64 ? pins package ? carrier no ? character ? = ? tray ? (default) ????????????????????? t ? = ? tape ? and ? reel package ? grade package ? type a ? = ? tqfp m ? = ? qfn c ? = ? ubga u ? = ? wlcsp u ? = ?\ 40 ?\? 85c ? matte ? sn ? plating ordering code flash (bytes) sram (bytes) package carrier type atsamd20e14a-au 16k 2k tqfp32 tray atsamd20e14a-aut ta p e & r e e l atsamd20e14a-mu qfn32 tray atsamd20e14a-mut ta p e & r e e l atsamd20e15a-au 32k 4k tqfp32 tray atsamd20e15a-aut ta p e & r e e l atsamd20e15a-mu qfn32 tray atsamd20e15a-mut ta p e & r e e l atsamd20e16a-au 64k 8k tqfp32 tray atsamd20e16a-aut ta p e & r e e l atsamd20e16a-mu qfn32 tray atsamd20e16a-mut ta p e & r e e l atsamd20e17a-au 128k 16k tqfp32 tray atsamd20e17a-aut ta p e & r e e l atsamd20e17a-mu qfn32 tray atsamd20e17a-mut ta p e & r e e l
5 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 2.2 sam d20g atsamd20e18a-au 256k 32k tqfp32 tray atsamd20e18a-aut ta p e & r e e l atsamd20e18a-mu qfn32 tray atsamd20e18a-mut ta p e & r e e l ordering code flash (bytes) sram (bytes) package carrier type ordering code flash (bytes) sram (bytes) package carrier type atsamd20g14a-au 16k 2k tqfp48 tray atsamd20g14a-aut ta p e & r e e l atsamd20g14a-mu qfn48 tray atsamd20g14a-mut ta p e & r e e l atsamd20g15a-au 32k 4k tqfp48 tray atsamd20g15a-aut ta p e & r e e l atsamd20g15a-mu qfn48 tray atsamd20g15a-mut ta p e & r e e l atsamd20g16a-au 64k 8k tqfp48 tray atsamd20g16a-aut ta p e & r e e l atsamd20g16a-mu qfn48 tray atsamd20g16a-mut ta p e & r e e l atsamd20g17a-au 128k 16k tqfp48 tray atsamd20g17a-aut ta p e & r e e l atsamd20g17a-mu qfn48 tray atsamd20g17a-mut ta p e & r e e l atsamd20g18a-au 256k 32k tqfp48 tray atsamd20g18a-aut ta p e & r e e l atsamd20g18a-mu qfn48 tray atsamd20g18a-mut ta p e & r e e l
6 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 2.3 sam d20j ordering code flash (bytes) sram (bytes) package carrier type atsamd20j14a-au 16k 2k tqfp64 tray atsamd20j14a-aut ta p e & r e e l atsamd20j14a-mu qfn64 tray atsamd20j14a-mut ta p e & r e e l ATSAMD20J15A-AU 32k 4k tqfp64 tray ATSAMD20J15A-AUt ta p e & r e e l atsamd20j15a-mu qfn64 tray atsamd20j15a-mut ta p e & r e e l atsamd20j16a-au 64k 8k tqfp64 tray atsamd20j16a-aut ta p e & r e e l atsamd20j16a-mu qfn64 tray atsamd20j16a-mut ta p e & r e e l atsamd20j17a-au 128k 16k tqfp64 tray atsamd20j17a-aut ta p e & r e e l atsamd20j17a-mu qfn64 tray atsamd20j17a-mut ta p e & r e e l atsamd20j18a-au 256k 32k tqfp64 tray atsamd20j18a-aut ta p e & r e e l atsamd20j18a-mu qfn64 tray atsamd20j18a-mut ta p e & r e e l
7 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 3. block diagram notes: 1. some products have different number of sercom instances, ti mer/counter instances, ptc signals and adc signals. refer to ?configuration summary? on page 3 for details. 6 x sercom 8 x timer counter real time counter ahb-apb bridge c m s high speed bus matrix port port watchdog timer serial wire swdio nvm controller 256/128/64/32/16kb flash s arm cortex-m0+ processor f max 48mhz swclk device service unit ahb-apb bridge a adc ain[19:0] vrefa ain[3:0] s 32/16/8/4/2kb ram m reset controller sleep controller clock controller power manager reset 8 x timer counter event system s 6 x sercom 2 analog comparators system controller xout xin xout32 xin32 osculp32k osc32k osc8m dfll48m bod33 xosc32k xosc vref generic clock x[15:0] y[15:0] peripheral touch controller peripheral access controller ahb-apb bridge b vrefp vout dac external interrupt controller peripheral access controller peripheral access controller extint[15:0] nmi gclk_io[7:0] s pin[3:0] wo[1:0] vrefb (see note1) cmp1:0] arm single cycle iobus controller
8 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 4. pinout 4.1 sam d20j pa00 1 pa01 2 pa02 3 pa03 4 pb04 5 pb05 6 gndana 7 vddana 8 pb06 9 pb07 10 pb08 11 pb09 12 pa04 13 pa05 14 pa06 15 pa07 16 pa08 17 pa09 18 pa10 19 pa11 20 vddio 21 gnd 22 pb10 23 pb11 24 pb12 25 pb13 26 pb14 27 pb15 28 pa12 29 pa13 30 pa14 31 pa15 32 vddio 48 gnd 47 pa25 46 pa24 45 pa23 44 pa22 43 pa21 42 pa20 41 pb17 40 pb16 39 pa19 38 pa18 37 pa17 36 pa16 35 vddio 34 gnd 33 pb22 49 pb23 50 pa27 51 reset 52 pa28 53 gnd 54 vddcore 55 vddin 56 pa30 57 pa31 58 pb30 59 pb31 60 pb00 61 pb01 62 pb02 63 pb03 64 digital pin analog pin oscillator ground input supply regulated output supply reset pin
9 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 4.2 sam d20g pa21 pa00 1 pa01 2 pa02 3 pa03 4 gndana 5 vddana 6 pb08 7 pb09 8 pa04 9 pa05 10 pa06 11 pa07 12 pa08 13 pa09 14 pa10 15 pa11 16 vddio 17 gnd 18 pb10 19 pb11 20 pa12 21 pa13 22 pa14 23 pa15 24 vddio 36 gnd 35 pa25 34 pa24 33 pa23 32 pa22 31 30 pa20 29 pa19 28 pa18 27 pa17 26 pa16 25 pb22 37 pb23 38 pa27 39 reset 40 pa28 41 gnd 42 vddcore 43 vddin 44 pa30 45 pa31 46 pb02 47 pb03 48 digital pin analog pin oscillator ground input supply regulated output supply reset pin
10 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 4.3 sam d20e pa00 1 pa01 2 pa02 3 pa03 4 pa04 5 pa05 6 pa06 7 pa07 8 vddana 9 gnd 10 pa08 11 pa09 12 pa10 13 pa11 14 pa14 15 pa15 16 pa25 24 pa24 23 pa23 22 pa22 21 pa19 20 pa18 19 pa17 18 pa16 17 pa27 25 reset 26 pa28 27 gnd 28 vddcore 29 vddin 30 pa30 31 pa31 32 digital pin analog pin oscillator ground input supply regulated output supply reset pin
11 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 5. i/o multiplexing and considerations 5.1 multiplexed signals each pin is by default controlled by the port as a general purpose i/o and alternatively it can be assigned to one of the peripheral functions a, b, c, d, e, f, g or h. to enable a peripheral function on a pin, the peripheral multiplexer enable bit in the pin configuration register corresponding to that pin (pincfgn.pmuxen, n = 0-31) in the port must be written to one. the selection of peripheral function a to h is done by writing to the peripheral multiplexing odd and even bits in the peripheral multiplexing register (p muxn.pmuxe/o) in the port. refer to !!!crs_port_top!!! for details on how to configure the i/o multiplexing. table 5-1 describes the peripheral signals multiplexed to the port i/o pins. table 5-1. port function multiplexing pin i/o pin supply pin type a b (1) c d e f g h sam d20e sam d20g sam d20j eic ref adc ac ptc dac sercom (2) tc (3) ac/gclk 1 1 1 pa00 vddana extint[0] sercom1/ pad[0] tc2/ wo[0] 2 2 2 pa01 vddana extint[1] sercom1/ pad[1] tc2/ wo[1] 3 3 3 pa02 vddana extint[2] ain[0] y[0] vout 4 4 4 pa03 vddana extint[3] adc/vrefa dac/vrefa ain[1] y[1] 5 pb04 vddana extint[4] ain[12] y[10] 6 pb05 vddana extint[5] ain[13] y[11] 9 pb06 vddana extint[6] ain[14] y[12] 10 pb07 vddana extint[7] ain[15] y[13] 7 11 pb08 vddana extint[8] ain[2] y[14] sercom4/ pad[0] tc4/ wo[0] 8 12 pb09 vddana extint[9] ain[3] y[15] sercom4/ pad[1] tc4/ wo[1] 5 9 13 pa04 vddana extint[4] adc/ vrefb ain[4] ain[0] y[2] sercom0/ pad[0] tc0/ wo[0] 6 10 14 pa05 vddana extint[5] ain[5] ain[1] y[3] sercom0/ pad[1] tc0/ wo[1] 7 11 15 pa06 vddana extint[6] ain[6] ain[2] y[4] sercom0/ pad[2] tc1/ wo[0] 8 12 16 pa07 vddana extint[7] ain[7] ain[3] y[5] sercom0/ pad[3] tc1/ wo[1] 11 13 17 pa08 vddio i 2 c nmi ain[16] x[0] sercom0/ pad[0] sercom2/ pad[0] tc0/ wo[0] 12 14 18 pa09 vddio i 2 c extint[9] ain[17] x[1] sercom0/ pad[1] sercom2/ pad[1] tc0/ wo[1] 13 15 19 pa10 vddio extint[10] ain[18] x[2] sercom0/ pad[2] sercom2/ pad[2] tc1/ wo[0] gclk_o[4] 14 16 20 pa11 vddio extint[11] ain[19] x[3] sercom0/ pad[3] sercom2/ pad[3] tc1/ wo[1] gclk_io[5] 19 23 pb10 vddio extint[10] sercom4/ pad[2] tc5/ wo[0] gclk_io[4] 20 24 pb11 vddio extint[11] sercom4/ pad[3] tc5/ wo[1] gclk_io[5] 25 pb12 vddio i 2 c extint[12] x[12] sercom4/ pad[0] tc4/ wo[0] gclk_io[6] 26 pb13 vddio i 2 c extint[13] x[13] sercom4/ pad[1] tc4/ wo[1] gclk_io[7] 27 pb14 vddio extint[14] x[14] sercom4/ pad[2] tc5/ wo[0] gclk_io[0]
12 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 note: 1. all analog pin functions are on peripheral function b. peri pheral function b must be selected to disable the digital con trol of the pin. 28 pb15 vddio extint[15] x[15] sercom4/ pad[3] tc5/ wo[1] gclk_io[1] 21 29 pa12 vddio i 2 c extint[12] sercom2/ pad[0] sercom4/ pad[0] tc2/ wo[0] ac/cmp[0] 22 30 pa13 vddio i 2 c extint[13] sercom2/ pad[1] sercom4/ pad[1] tc2/ wo[1] ac/cmp[1] 15 23 31 pa14 vddio extint[14] sercom2/ pad[2] sercom4/ pad[2] tc3/ wo[0] gclk_io[0] 16 24 32 pa15 vddio extint[15] sercom2/ pad[3] sercom4/ pad[3] tc3/ wo[1] gclk_io[1] 17 25 35 pa16 vddio i 2 c extint[0] x[4] sercom1/ pad[0] sercom3/ pad[0] tc2/ wo[0] gclk_io[2] 18 26 36 pa17 vddio i 2 c extint[1] x[5] sercom1/ pad[1] sercom3/ pad[1] tc2/ wo[1] gclk_io[3] 19 27 37 pa18 vddio extint[2] x[6] sercom1/ pad[2] sercom3/ pad[2] tc3/ wo[0] ac/cmp[0] 20 28 38 pa19 vddio extint[3] x[7] sercom1/ pad[3] sercom3/ pad[3] tc3/ wo[1] ac/cmp[1] 39 pb16 vddio i 2 c extint[0] sercom5/ pad[0] tc6/ wo[0] gclk_io[2] 40 pb17 vddio i 2 c extint[1] sercom5/ pad[1] tc6/ wo[1] gclk_io[3] 29 41 pa20 vddio extint[4] x[8] sercom5/ pad[2] sercom3/ pad[2] tc7/ wo[0] gclk_io[4] 30 42 pa21 vddio extint[5] x[9] sercom5/ pad[3] sercom3/ pad[3] tc7/ wo[1] gclk_io[5] 21 31 43 pa22 vddio i 2 c extint[6] x[10] sercom3/ pad[0] sercom5/ pad[0] tc4/ wo[0] gclk_io[6] 22 32 44 pa23 vddio i 2 c extint[7] x[11] sercom3/ pad[1] sercom5/ pad[1] tc4/ wo[1] gclk_io[7] 23 33 45 pa24 vddio extint[12] sercom3/ pad[2] sercom5/ pad[2] tc5/ wo[0] 24 34 46 pa25 vddio extint[13] sercom3/ pad[3] sercom5/ pad[3] tc5/ wo[1] 37 49 pb22 vddio extint[6] sercom5/ pad[2] tc7/ wo[0] gclk_io[0] 38 50 pb23 vddio extint[7] sercom5/ pad[3] tc7/ wo[1] gclk_io[1] 25 39 51 pa27 vddio extint[15] gclk_io[0] 27 41 53 pa28 vddio extint[8] gclk_io[0] 31 45 57 pa30 vddio extint[10] sercom1/ pad[2] tc1/ wo[0] swclk gclk_io[0] 32 46 58 pa31 vddio extint[11] sercom1/ pad[3] tc1/ wo[1] swdio (4) 59 pb30 vddio i 2 c extint[14] sercom5/ pad[0] tc0/ wo[0] 60 pb31 vddio i 2 c extint[15] sercom5/ pad[1] tc0/ wo[1] 61 pb00 vddana extint[0] ain[8] y[6] sercom5/ pad[2] tc7/ wo[0] 62 pb01 vddana extint[1] ain[9] y[7] sercom5/ pad[3] tc7/ wo[1] 47 63 pb02 vddana extint[2] ain[10] y[8] sercom5/ pad[0] tc6/ wo[0] 48 64 pb03 vddana extint[3] ain[11] y[9] sercom5/ pad[1] tc6/ wo[1] table 5-1. port function multiplexing (continued) pin i/o pin supply pin type a b (1) c d e f g h sam d20e sam d20g sam d20j eic ref adc ac ptc dac sercom (2) tc (3) ac/gclk
13 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 2. only some pins can be used in sercom i 2 c mode. see the type column for using a sercom pin in i 2 c mode. refer to the !!!crs_elchar_i2c_pins!!! for details on the i 2 c pin characteristics 3. note that tc6 and tc7 are not supported on the sam d20g. refer to ?configuration summary? on page 3 for details. 4. this function is only activat ed in the presence of a debugger 5.2 other functions 5.2.1 oscillator pinout the oscillators are not mapped to the normal port functions and their multiplexing are controlled by registers in the system controller (sysctrl). refer to !!!crs_sysctrl_top!!! for more information. 5.2.2 serial wire debug interface pinout after reset, swclk functionality is selected for pin pa30 to allow for debugger probe detection. the application software can switch the swclk functionality of pa30 to gpio (or other peripherals) during runtime. pa31, by default, is config- ured like other normal i/o pins and will automatically swit ch to swdio function when a debugger cold-plugging or hot- plugging is detected. when the device is put in debug mode, application software accesses to pa30 and pa31 port registers are ignored. refer to !!!crs_dsu_top!!! for more information. oscillator supply signal i/o pin xosc vddio xin pa14 xout pa15 xosc32k vddana xin32 pa00 xout32 pa01 signal supply i/o pin swclk vddio pa30 swdio vddio pa31
14 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 6. product mapping figure 6-1. sam d20 product mapping this figure represents the full configuration of the atmel ? sam d20 with maximum flash and sram capabilities and a full set of peripherals. refer to the ?configuration summary? on page 3 for details. code sram undefined peripherals reserved undefined global memory space 0x00000000 0x20000000 0x20008000 0x40000000 0x43000000 0x60000000 0x60000200 0xffffffff internal sram sram 0x20000000 0x20008000 ahb-apb bridge a ahb-apb bridge b ahb-apb bridge c peripherals 0x40000000 0x41000000 0x42000000 0x42ffffff reserved pac0 pm sysctrl gclk wdt rtc eic ahb-apb bridge a 0x40000000 0x40000400 0x40000800 0x40000c00 0x40001000 0x40001400 0x40001800 0x40ffffff 0x40001c00 ahb-apb bridge b reserved pac1 dsu nvmctrl port 0x41000000 0x41002000 0x41004000 0x41004400 0x41ffffff 0x41004800 internal flash code 0x00000000 0x00040000 0x1fffffff reserved sercom5 pac2 evsys sercom0 sercom1 sercom2 sercom3 sercom4 ahb-apb bridge c tc7 tc0 tc1 tc2 tc3 tc4 tc5 tc6 adc ac 0x42000000 0x42000400 0x42000800 0x42000c00 0x42001000 0x42001400 0x42001800 0x42002000 0x42001c00 0x42003000 0x42003400 0x42003800 0x42003c00 0x42004000 0x42004400 0x42004800 reserved 0x42ffffff dac 0x42004c00 0x42002400 0x42002800 0x42002c00 ptc 0x42005000 reserved system 0xe0000000 scs reserved reserved rom table reserved system 0xe0000000 0xe000e000 0xe000f000 0xe00ff000 0xe0100000 0xffffffff
15 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 7. processor and architecture 7.1 cortex-m0+ processor the atmel ? sam d20 implements the arm ? cortex ? -m0+ processor, which is based on the armv6 architecture and thumb ? -2 isa. the cortex m0+ is 100% instruction set compatible with its predecessor, the cortex-m0 processor, and upward compatible with the cortex-m3 and cortex-m4 proces sors. the arm cortex-m0+ implemented is revision r0p1. for more information, refer to www.arm.com . 7.1.1 cortex-m0+ configuration note: 1. all software run in privileged mode only the arm cortex-m0+ processor has two bus interfaces: z single 32-bit amba ? 3 ahb-lite? system interface that provides connections to peripherals and all system memory, including flash and ram z single 32-bit i/o port bus interfacing to the port with one-cycle loads and stores feature configurable option sam d20 configuration interrupts external interrupts 0-32 32 data endianness little-endian or big-endian little-endian systick timer present or absent present number of watchpoint comparators 0, 1, 2 2 number of breakpoint comparators 0, 1, 2, 3, 4 4 halting debug support present or absent present multiplier fast or small fast (single cycle) single-cycle i/o port present or absent present wake-up interrupt controller supported or not supported not supported vector table offset register present or absent present unprivileged/privileged support present or absent absent memory protection unit not present or 8-region not present reset all registers present or absent absent (1) instruction fetch width 16-bit only or mostly 32-bit 32-bit
16 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 8. packaging information 8.1 thermal considerations 8.1.1 thermal resistance data table 8-1 summarizes the thermal resistance data depending on the package. table 8-1. thermal resistance data 8.1.2 junction temperature the average chip-junction temperature, t j , in c can be obtained from the following equations: equation 1 equation 2 where: z ja = package thermal resistance, junction-to-ambient (c/w), provided in table 8-1 z jc = package thermal resistance, junction-to-case thermal resistance (c/w), provided in table 8-1 z heatsink = cooling device thermal resistance (c/w), provided in the manufacturer datasheet z p d = device power consumption (w) z t a = ambient temperature (c) from ?equation 1? , the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. if a cooling device is to be fitted on the chip, ?equation 2? should be used to compute the resulting average chip- junction temperature t j in c. package type ja jc 32-pin tqfp 68 c/w 25.8 c/w 48-pin tqfp 78.8 c/w 12.3 c/w 64-pin tqfp 66.7 c/w 11.9 c/w 32-pin qfn 37.2 c/w 3.1 c/w 48-pin qfn 33 c/w 11.4 c/w 64-pin qfn 33.5 c/w 11.2 c/w t j t a p d ja () + = t j t a p d heatsink jc + () () + =
17 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 8.2 package drawings 8.2.1 64-pin tqfp table 8-2. device and package maximum weight table 8-3. package characteristics table 8-4. package reference 300 mg moisture sensitivity level msl3 jedec drawing reference ms-026 jesd97 classification e3
18 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 8.2.2 64-pin qfn note: the exposed die attached pad is not connected inside the device. table 8-5. device and package maximum weight table 8-6. package characteristics table 8-7. package reference 200 mg moisture sensitivity level msl3 jedec drawing reference mo-220 jesd97 classification e3
19 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 8.2.3 48-pin tqfp table 8-8. device and package maximum weight table 8-9. package characteristics table 8-10. package reference 140 mg moisture sensitivity level msl3 jedec drawing reference ms-026 jesd97 classification e3
20 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 8.2.4 48-pin qfn note: the exposed die attached pad is not connected inside the device. table 8-11. device and package maximum weight table 8-12. package characteristics table 8-13. package reference 140 mg moisture sensitivity level msl3 jedec drawing reference mo-220 jesd97 classification e3
21 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 8.2.5 32-pin tqfp table 8-14. device and package maximum weight table 8-15. package characteristics table 8-16. package reference 100 mg moisture sensitivity level msl3 jedec drawing reference ms-026 jesd97 classification e3
22 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 8.2.6 32-pin qfn note: the exposed die attached pad is connected inside the device to gnd and gndana connected together. table 8-17. device and package maximum weight table 8-18. package characteristics table 8-19. package reference 90 mg moisture sensitivity level msl3 jedec drawing reference mo-220 jesd97 classification e3
23 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 8.3 soldering profile table table 8-20 gives the recommended soldering profile from j-std-20. table 8-20. soldering profile a maximum of three reflow passes is allowed per component. ___ rev ___217270 profile feature green package average ramp-up rate (217c to peak) 3c/s max. preheat temperature 175c 25c 150-200c time maintained above 217c 60-150s time within 5c of actual peak temperature 30s peak temperature range 260c ramp-down rate 6c/s max time 25c to peak temperature 8 minutes max.
24 atmel sam d20 [datasheet summary] 42129js?sam?12/2013 table of contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1. configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 sam d20e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 sam d20g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 sam d20j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4. pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 sam d20j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 sam d20g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 sam d20e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. i/o multiplexing and considerations . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 multiplexed signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2 other functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6. product mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7. processor and architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 cortex-m0+ processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8. packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.1 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.2 package drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.3 soldering profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
atmel corporation 1600 technology drive san jose, ca 95110 usa tel: (+1) (408) 441-0311 fax: (+1) (408) 487-2600 www.atmel.com atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong roa kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan g.k. 16f shin-osaki kangyo bldg 1-6-4 osaki, shinagawa-ku tokyo 141-0032 japan tel: (+81) (3) 6417-0300 fax: (+81) (3) 6417-0370 ? 2013 atmel corporation. all rights reserved. / rev.: 42129js?sam?12/2013 disclaimer: the information in this document is provided in co nnection with atmel products. no lic ense, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. exc ept as set forth in the atmel terms and conditions of sales locat ed on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not li mited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any d irect, indirect, consequential, punitive, special or incide ntal damages (including, without limitation, damages for loss and profits, business i nterruption, or loss of information) arising out of the us e or inability to use this document, even if at mel has been advised of the possibility of suc h damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and products descriptions at any time without notice. atmel does not make any commitment to update th e information contained herein. un less specifically provided oth erwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products are not intended, authorized, or warranted for use as components in applications intend ed to support or sustain life. atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , qtouch ? , and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. arm ? , cortex ? and others are registered trademarks or trademarks of arm ltd. other terms and product names may be trademarks of others.

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